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Features
* Fully Integrated 2.4 GHz-band Transceiver * -101 dBm Receiver Sensitivity * Low Current Consumption (Typical Values) - SLEEP = 0.1 A - TRX_OFF = 1.7 mA - RX_ON = 16 mA - BUSY_TX = 17 mA (max. PTX) * Power Supply Range 1.8V - 3.6V - Internal LDO Voltage Regulators - Battery Monitor * SPI Slave Interface * Baseband Signal Processing Compliant with IEEE 802.15.4 - SFD Detection, Spreading/De-spreading, Framing - 128-byte FIFO for TRX * Integrated Crystal Oscillator, 16 MHz * Digital RSSI Register, 5-bit Value * Fast Power-up Time < 1 msec * Programmable TX Output Power from -17 dBm up to 3 dBm * Integrated LNA * Low External Component Count - Antenna - Reference Crystal - De-coupling Capacitors * Integrated TX/RX Switch * Integrated PLL Loop Filter * Automatic VCO and Filter Calibration * 32-pin Low-profile Lead-free Plastic QFN Package 5 mm x 5 mm x 0.9 mm * Compliant to EN 300 440/328, FCC-CFR-47 Part 15 * Compliant to IEEE 802.15.4
ZigBeeTM/IEEE 802.15.4Transceiver
AT86RF230
Applications
* 802.15.4 Transceiver * Transceiver for ZigBee System Solutions
Description
The AT86RF230 is a low-power 2.4 GHz transceiver specially designed for low cost ZigBee/IEEE802.15.4 applications. The AT86RF230 is a true SPI-toantenna solution. All RF-critical components except the antenna, crystal and decoupling capacitors are integrated on-chip.
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Table of contents
1. 2. 3. Abbreviations ...................................................................................................................................................4 General Circuit Description..............................................................................................................................5 Technical Parameters......................................................................................................................................6 3.1. Absolute Maximum Ratings.........................................................................................................................6 3.2. Recommended Operating Range................................................................................................................6 3.3. Digital Pin Specifications .............................................................................................................................6 3.4. General RF Specifications...........................................................................................................................7 3.5. Transmitter Specifications ...........................................................................................................................7 3.6. Receiver Specifications ...............................................................................................................................8 3.7. Current Consumption Specifications ...........................................................................................................9 3.8. SPI Timing Specifications............................................................................................................................9 3.9. Crystal Parameter Specifications ..............................................................................................................10 4. Basic Operating Modes .................................................................................................................................11 4.1. Configuration .............................................................................................................................................11 4.2. Basic Operating Mode Description............................................................................................................12 4.2.1. P_ON ....................................................................................................................................................12 4.2.2. SLEEP...................................................................................................................................................12 4.2.3. TRX_OFF..............................................................................................................................................12 4.2.4. PLL_ON ................................................................................................................................................12 4.2.5. RX_ON and BUSY_RX .........................................................................................................................13 4.2.6. RX_ON_NOCLK ...................................................................................................................................13 4.2.7. BUSY_TX..............................................................................................................................................13 4.3. Basic Mode Timing ....................................................................................................................................13 4.3.1. Wake-up Procedure ..............................................................................................................................13 4.3.2. Transition from PLL_ON via BUSY_TX to RX_ON...............................................................................14 4.3.3. State Transition Timing .........................................................................................................................15 5. Extended Operating Modes ...........................................................................................................................16 5.1. Peer-to-peer Network Support ..................................................................................................................16 5.2. Configuration .............................................................................................................................................18 5.3. Extended Operation Mode Description .....................................................................................................18 5.3.1. RX_AACK_ON ......................................................................................................................................18 5.3.2. TX_ARET_ON.......................................................................................................................................18 5.3.3. RX_AACK_NOCLK ...............................................................................................................................19 6. Functional Description ...................................................................................................................................20 6.1. RSSI/Energy Detection .............................................................................................................................20 6.2. Link Quality Indication ...............................................................................................................................20 6.3. Clear Channel Assessment.......................................................................................................................20 6.4. Voltage Regulators ....................................................................................................................................20 6.5. Battery Monitor ..........................................................................................................................................21 6.6. Crystal Oscillator .......................................................................................................................................22 6.7. PLL Frequency Synthesizer ......................................................................................................................23 6.8. Automatic Filter Tuning .............................................................................................................................24 7. PHY to Micro-Controller Interface..................................................................................................................25 7.1. SPI Protocol...............................................................................................................................................25 7.2. Register Access Mode (Short Mode) ........................................................................................................26 7.3. Frame Buffer Access Modes (Long Modes)..............................................................................................27 7.4. Frame Receive Procedure ........................................................................................................................28 7.5. Frame Transmit Procedure .......................................................................................................................28 7.6. Sleep/Wake-up and Transmit Signal.........................................................................................................29 7.7. Interrupt Logic............................................................................................................................................30
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8. 9. 10. 10.1. 10.2. 10.3. 10.4. 10.5. 11. 12. 13. 14. 15. 16.
Control Registers ...........................................................................................................................................31 Application Circuit ..........................................................................................................................................42 Pin Configuration ...........................................................................................................................................44 Pin-out Diagram.........................................................................................................................................45 Decoupling.................................................................................................................................................45 Analog Pins ...............................................................................................................................................45 RF Pins......................................................................................................................................................45 Digital Pins.................................................................................................................................................46 Ordering Information......................................................................................................................................47 Soldering Information.....................................................................................................................................47 Package Thermal Properties .........................................................................................................................47 Package Drawing - 32QN1 ...........................................................................................................................48 References.....................................................................................................................................................49 Revisions .......................................................................................................................................................49
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1. Abbreviations
AACK ACK ADC AGC ARET AVREG BATMON BBP BPF CCA CLKM CRC CSMA DCLK DCU DVREG ED ESD EVM FIFO FTN GPIO LDO LNA LO LQI LSB MSB MSK O-QPSK PA PAN PER PHY PLL POR PPF PSDU QFN RF RSSI RX SFD SPI SRAM TX VCO VREG XOSC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Auto acknowledge Acknowledge Analog-to-digital converter Automatic gain control Auto retry Analog voltage regulator Battery monitor Base-band processor Complex band-pass filter Clear channel assessment Clock main Cyclic redundancy check Carrier sense multiple access Digital clock Delay calibration unit Digital voltage regulator Energy detection Electro static discharge Error vector magnitude First in first out Automatic filter tuning General purpose input output Low-drop output Low-noise amplifier Local oscillator Link-quality indication Least significant bit Most significant bit Minimum shift keying Offset-quadrature phase shift keying Power amplifier Personal area network Packet error rate Physical layer Phase-locked loop Power-on reset Poly-phase filter PHY service data unit Quad flat no-lead package Radio frequency Received signal strength indicator Receiver Start frame delimiter Serial peripheral interface Static random access memory Transmitter Voltage controlled oscillator Voltage regulator Crystal oscillator
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2. General Circuit Description
XTAL1 XTAL2
Analog Domain
TX power control DCLK XOSC
Digital Domain
AVREG BATMON
DVREG IRQ
FTN
PA
Frequency Synthesis
TX Data
TX BBP
SEL MISO
RFP RFN
I
Control Logic/ Configuration Registers
SPI Slave Interface
SCLK MOSI
LNA
PPF
Q
BPF
Limiter
ADC
RX BBP
TRX Data Buffer CLKM
RSSI AGC
5
SLP_TR RSTN
Figure 2-1.
Block Diagram of AT86RF230
This single-chip RF transceiver provides a complete radio interface between the antenna and the micro-controller. It comprises the analog radio part, digital demodulation including time and frequency synchronization and data buffering. The number of external components is minimized so that only the antenna, the crystal and four decoupling capacitors are required. The bidirectional differential antenna pins are used in common for RX and TX, so no external antenna switch is needed. The transceiver block diagram is shown in Figure 2-1. The receiver path is based on a low-IF topology. The channel filter consists of three single side-band active RC resonators forming a 2 MHz band-pass filter with a st Butterworth characteristic centered at 2 MHz. Two 1 -order high-pass filters were added to the signal path to achieve capacitive coupling at the single side-band filter (SSBF) output to suppress DC offset and integrator feedback at the limiter amplifier. The 3-stage limiter amplifier provides sufficient gain to overcome the DC offset of the succeeding single channel ADC and generates a digital RSSI signal with 3 dB granularity. The low-IF signal is sampled at 16 MHz with 1-bit resolution and applied to the digital signal processing part. Direct VCO modulation is used to generate the transmit signal. The modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32-length block coding (spreading). This is equivalent to minimum shift keying (MSK) when transforming the spreading code sequences appropriately. The modulation signal is applied to both the VCO and the fractional-N PLL to ensure the coherent phase modulation required for demodulation as an OQPSK signal. The frequency-modulated LO signal is fed to the power amplifier. Two on-chip low-dropout voltage regulators provide the analog and digital 1.8V supply. The SPI interface and the control registers will retain their settings in SLEEP mode when the regulators are turned off. The RX and TX signal processing paths are highly integrated and optimized for low power consumption.
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3. Technical Parameters
3.1. Absolute Maximum Ratings
Note: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
No 3.1.1 3.1.2 Parameter Storage temperature Lead temperature Symbol Tstor Tlead Min -50 Typ Max 150 260 Unit C C T = 10s (soldering profile compliant with IPC/JEDEC J-STD-020B) Compl. to [2], passed 4 kV Compl. to [3], Compl. to [4], passed 750V Conditions/Notes
3.1.3
ESD-protection
VESD
2 200 500 +10 -0.3 -0.3 Vdd+0.3 3.6 2
kV V V dBm V V
3.1.4 3.1.5 3.1.6
Input RF level Voltage on all pins (except pins 13, 14, 29) Voltage on pins 13, 14, 29
PRF
Table 3-1.
Absolute Maximum Ratings
3.2.
No 3.2.1 3.2.2
Recommended Operating Range
Parameter Operating temperature range Supply voltage Symbol Top Vdd Min -40 1.8 Typ Max +85 3.6 Unit C V Conditions/Notes
Table 3-2.
Operating Range
3.3.
No 3.3.1 3.3.2 3.3.3 3.3.4
Digital Pin Specifications
Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage Symbol VIH VIL VOH VOL Vdd - 0.4 0.4 Min Vdd - 0.4 0.4 Typ Max Unit V V V V For all output current loads defined in register TRX_CTR_0 For all output current loads defined in register TRX_CTR_0 Conditions/Notes
Test Conditions (unless otherwise stated): Tamb = 25 C
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No 3.3.5
Parameter Controller clock frequency (CLKM)
Symbol fCLKM
Min
Typ 0 1 2 4 8 16
Max
Unit MHz MHz MHz MHz MHz MHz
Conditions/Notes Programmable in register TRX_CTRL_0
Table 3-3.
Digital Pin Specifications
The capacitive load should not be larger than 50 pF for all I/Os when using the default driver strength settings. Generally, large load capacitances will increase the overall current consumption.
3.4.
No 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6
General RF Specifications
Parameter Frequency range Bit rate Chip rate Reference oscillator frequency Reference oscillator settling time Reference frequency accuracy for correct functionality 20 dB bandwidth B20dB -60 Symbol f fbit fchip fclk Min 2405 250 2000 16 0.5 1 +60 Typ Max 2480 Unit MHz kbit/s As specified in [1] Conditions/Notes
Test Conditions (unless otherwise stated): Vdd = 3V, f = 2.45 GHz, Tamb = 25 Measurement setup see Figure 9-1 C,
kchip/s As specified in [1] MHz ms ppm Leaving SLEEP state to clock available at pin CLKM 40 ppm is required by [1]
3.4.7
2.8
MHz
Table 3-4:
General RF Parameters
3.5.
No 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6
Transmitter Specifications
Parameter Nominal output power Output power range Output power accuracy TX Return loss EVM Harmonics 2nd harmonic 3rd harmonic 10 8 -38 -45 Symbol PTX Min 0 Typ 3 20 3 Max 6 Unit dBm dB dB dB 100 differential impedance, PTX = 3 dBm Conditions/Notes Max. value 16 steps (register PHY_TX_PWR)
Test Conditions (unless otherwise stated): Vdd = 3V, f = 2.45 GHz, Tamb = 25 Measurement setup see Figure 9-1 C,
%rms Channel number = 20 dBm dBm
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No 3.5.7
Parameter Spurious emissions 30 - 1000 MHz >1 - 12.75 GHz 1.8 - 1.9 GHz 5.15 - 5.3 GHz
Symbol
Min
Typ
Max -36 -30 -47 -47
Unit dBm dBm dBm dBm
Conditions/Notes Complies with EN 300 440, FCC-CFR-47 part 15, ARIB STD-66, RSS-210
Table 3-5.
TX Parameters
3.6.
No 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.6.7 3.6.8 3.6.9
Receiver Specifications
Parameter Receiver sensitivity Return loss Noise figure Maximum RX input level Adjacent channel rejection -5 MHz Adjacent channel rejection +5 MHz Alternate adjacent channel rejection -10 MHz Alternate adjacent channel rejection +10 MHz Spurious emissions LO leakage 30 - 1000 MHz 1 - 12.75 GHz -300 IIP3 -9 NF Symbol Min Typ -101 10 6 10 34 36 52 53 Max Unit dBm dB dB dBm dBm dBm dBm dBm PER 1%, PSDU length of 20 octets PER 1%, PSDU length of 20 octets, PRF = -82 dBm PER 1%, PSDU length of 20 octets, PRF = -82 dBm PER 1%, PSDU length of 20 octets, PRF = -82 dBm PER 1%, PSDU length of 20 octets, PRF = -82 dBm Conditions/Notes AWGN channel, PER1%, PSDU length of 20 octets 100 differential impedance
Test Conditions (unless otherwise stated): Vdd = 3V, f = 2.45 GHz, Tamb = 25C, Measurement setup see Figure 9-1
-75 -57 -47 300
dBm dBm dBm kHz dB Sensitivity loss < 2 dB At maximum gain Offset freq. interf. 1 = 5 MHz Offset freq. interf. 2 = 10 MHz At maximum gain Offset freq. interf. 1 = 60 MHz Offset freq. interf. 2 = 62 MHz Tolerance within gain step
3.6.10 TX/RX carrier frequency offset 3.6.11 3 -order intercept point
rd
3.6.12 2 -order intercept point
nd
IIP2
24
dB
3.6.13 RSSI accuracy absolute 3.6.14 RSSI dynamic range 3.6.15 RSSI resolution 3.6.16 Minimum RSSI value 3.6.17 Maximum RSSI value
-5 84 3 0 28
5
dB dB dB
PRF < -91 dBm PRF > -10 dBm
Table 3-6.
RX Parameters
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3.7.
Current Consumption Specifications
Test Conditions (unless otherwise stated): Vdd = 3V, Tamb = 25C, CLKM = OFF, Measurement setup see Figure 9-1
No 3.7.1 Parameter Supply current transmit mode Symbol IBUSY_TX Min Typ 17 15 13 10 Max Unit mA mA mA mA Conditions/Notes PTX = 3 dBm PTX = 1 dBm PTX = -3 dBm PTX = -17 dBm (the current consumption will be reduced by approx. 2 mA at Vdd = 1.8V for each output power level) State: RX_ON State: TRX_OFF State: SLEEP
3.7.2 3.7.3 3.7.4
Supply current receive mode Supply current TRX_OFF mode Supply current SLEEP mode
IRX_ON ITRX_OFF ISLEEP
16 1.7 0.1
mA mA A
Table 3-7.
Current Consumption
3.8.
No 3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6 3.8.7 3.8.8 3.8.9
SPI Timing Specifications
Parameter SCLK frequency (synchronous) SCLK frequency (asynchronous) SEL low to MISO active SCLK to MISO out MOSI setup time MOSI hold time LSB last byte to MSB next byte SEL high to MISO tristate SLP_TR pulse width t1 t2 t3 t4 t5 t6 t7 65 48 10 10 250 10 Symbol Min Typ Max 8 7.5 180 Unit MHz MHz ns ns ns ns ns ns ns data hold time Conditions/Notes
Test Conditions (unless otherwise stated): Vdd = 3V, Tamb = 25C
Table 3-8.
SPI Timing Parameters (see Figure 7-2)
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3.9.
No 3.9.1 3.9.2 3.9.3 3.9.4
Crystal Parameter Specifications
Parameter Crystal frequency Load capacitance Static capacitance Series resistance Symbol f0 CL C0 R1 8 Min Typ 16 14 7 100 Max Unit MHz pF pF Conditions/Notes
Table 3-9.
Crystal Parameter Specifications
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4. Basic Operating Modes
This section summarizes all features that are needed to provide the basic functionality of a transceiver system, such as receiving and transmitting frames, and powering down. These basic operating modes are sufficient for ZigBee applications and are shown in Figure 4-1.
P_ON
(Power-on after VDD)
XOSC=ON Pull=ON
SLEEP
(Sleep Mode)
XOSC=OFF Pull=OFF
1
2
FORCE_TRX_OFF
12
TRX_OFF
(Clock Mode)
XOSC=ON Pull=OFF
TR =0 SL P_ TR =1
3
SL P_
(all modes except SLEEP)
O N
RX _
6 Frame Start Frame End
TR X_ O
FF
X TR _O FF
13
RST=0
(all modes except P_ON)
ON L_ PL
7
5
X_ TR FF O
4 Frame End 10 TX_START SLP_TR=1
BUSY_RX
(Receive Mode)
CLKM=ON
RX_ON
(Rx Listen Mode)
CLKM=ON
8
RX_ON PLL_ON
PLL_ON
(PLL Mode) 9
11
BUSY_TX
(Transmit Mode)
Frame Start
S
_T LP
S
R=
1
R =0
_T LP
RX_ON_NOCLK
(Rx Listen Mode)
CLKM=OFF
Legend: Blue: SPI Write to Register TRX_STATE (0x02) Red: Control signals via IC Pin Green: Event
Figure 4-1.
Basic Operating Modes State Diagram
4.1.
Configuration
The operating modes are controlled by two signal pins and the SPI access to register 0x02 (TRX_STATE). The successful state change can be confirmed by reading the transceiver state from register 0x01 (TRX_STATUS). The pin SLP_TR is used to enter SLEEP mode where current consumption is minimal (leakage current only) and to wake-up the transceiver. The pin RST provides a reset of all registers and forces the transceiver into TRX_OFF mode, if the IC is not in the P_ON mode.
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The state change commands FORCE_TRX_OFF and TRX_OFF both lead to a transition into TRX_OFF state. If the transceiver is in the BUSY_RX or BUSY_TX state, the command FORCE_TRX_OFF interrupts the active receiving or transmitting process, and forces an immediate transition. On the other hand, a TRX_OFF command is stored until a frame currently being received or transmitted is finished. After the end of the frame, the transition to TRX_OFF is performed.
4.2.
4.2.1.
Basic Operating Mode Description
P_ON
When the external supply voltage (VDD) is first supplied to the transceiver IC, the system is in the P_ON (Poweron) mode. In this mode, the crystal oscillator is activated and the master clock for the controller is provided at the CLKM pin after a delay of 128s to ensure a steady state of the crystal oscillator. All digital inputs have pull-up or pull-down resistors (see Table 10-3). This is necessary to support controllers where GPIO signals are undefined after reset. The input pull-up and pull-down resistors are disabled when the transceiver leaves the P_ON state. A valid SPI write access to the register TRX_STATE with the values TRX_OFF or FORCE_TRX_OFF is necessary to leave the P_ON state. Prior to leaving P_ON, the controller must set the pins to the default operating values: SLP_TR = 0 and RST = 1 . An on-chip power-on-reset sets the all register to its default values. A dedicated reset signal from the controller at the pin RST is not necessary, but recommended for HW/SW synchronization reasons.
4.2.2.
SLEEP
In SLEEP mode, the entire transceiver IC is disabled. No circuitry is running. The current consumption in this mode is leakage current only. This mode can only be entered from state TRX_OFF, when the pin SLP_TR is set to "1". There is no way to switch the transceiver to SLEEP mode via SPI register access. Leaving this state is possible in two ways: Setting the SLP_TR pin to "0" returns the transceiver to the TRX_OFF mode without resetting any registers. Using RST = 0 resets the SPI and configuration registers to their default values and forces the IC into the TRX_OFF mode.
4.2.3.
TRX_OFF
The TRX_OFF mode provides the master clock for the controller in synchronous operation mode, allowing the software to run without the need for the radio to be powered on. The pins SLP_TR and RST are enabled for mode control. In this mode, the SPI interface and crystal oscillator are active. The voltage regulator is enabled and provides 1.8V to the digital core for have access to the frame data buffers. The transition from P_ON to TRX_OFF mode is described in section 4.2.1.
4.2.4.
PLL_ON
Entering the PLL_ON mode from TRX_OFF will first enable the analog voltage regulator. After the voltage regulator has settled, the PLL frequency synthesizer is enabled. When the PLL has settled at the receive frequency, a successful PLL lock is indicated by an interrupt request at the IRQ pin. During PLL_ON mode, the command RX_ON via register 0x02 (TRX_STATE) sets the transceiver to RX_ON mode, even if the PLL is not yet settled.
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4.2.5.
RX_ON and BUSY_RX
The RX_ON mode enables the analog and digital receiver blocks and the PLL frequency synthesizer. The transition from TRX_OFF mode to RX_ON mode is started by setting the TRX_STATE to RX_ON via a SPI write access to register 0x02 (TRX_STATE). The receive mode is internally divided into RX_ON mode and BUSY_RX mode. There is no difference between the modes with respect to the analog radio part. During RX_ON mode, only the preamble detection of the digital signal processing is running. When a preamble is detected, the digital receiver is turned on, switching to the BUSY_RX mode. SLP_TR = 1 is only evaluated in RX_ON mode. When receiving a frame in BUSY_RX mode, the SLP_TR pin has no effect.
4.2.6.
RX_ON_NOCLK
If the radio is listening for an incoming frame and the controller is not running an application, the controller can be powered down to decrease the total system power consumption. This special power-down scenario for controllers running in synchronous mode is supported by the AT86RF230 using the state RX_ON_NOCLK. This state can only be entered by setting SLP_TR = 1 while the IC is in the RX_ON mode. The CLKM pin will then be disabled 35 clock cycles after the rising edge at the SLP_TR pin. This will enable the controller to complete its power-down sequence. The reception of a frame is signalized to the controller by a RX_START IRQ (see Figure 7-13). The clock CLKM is turned on once again and the transceiver enters the BUSY_RX state. The end of the transaction is signaled to the controller by an TRX_END interrupt. After the transaction has been completed, the transceiver will enter the RX_ON state. The transceiver will only re-enter the RX_ON_NOCLK state when the SLP_TR has been reset to "0", and afterwards set to "1" again. If the transceiver is in the RX_ON_NOCLK state, and the SLP_TR pin is reset to "0", it will enter the RX _ON state, and it will again start to supply the micro-controller with the clock signal.
4.2.7.
BUSY_TX
Transmitting can only be started from PLL_ON mode. There are two ways to start transmitting: using pin SLP_TR = 1 or SPI command TX_START in register 0x02 (TRX_STATE). Either of these will cause the IC to enter BUSY_TX mode. During the transition to BUSY_TX mode, the PLL frequency shifts 1.5 MHz to enable the different LO frequencies needed between receive and transmit modes. Transmission of the first data chip of the preamble is delayed by 16 s to allow PLL settling and PA ramping. When the end of the frame has been transmitted, the IC will automatically turn off the power amplifier and transition from the BUSY_TX mode to the PLL_ON mode. The PLL settles to the receiver LO frequency (-1.5 MHz frequency step). If the frame transmission was initiated by setting the pin SLP_TR to "1", a new transmission will only be started when the pin SLP_TR has been reset to "0" and afterwards to set to "1" again.
4.3.
4.3.1.
Basic Mode Timing
Wake-up Procedure
The following paragraphs depict the method of switching from one mode to another.
The wake-up procedure from SLEEP mode is shown in Figure 4-2. Deasserting the pin SLP_TR enables the crystal oscillator. After approximately 0.3 - 0.5 ms, the internal clock signal is available. After 128 s the clock signal is delivered at the CLKM pin providing the master clock to the 13
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micro-controller. An additional 256 s timer ensures that frequency stability is sufficient to drive filter tuning (FTN) and the PLL. After band-gap voltage and digital voltage regulator settling, the transceiver enters the TRX_OFF state and waits for further commands.
0 ~400 500 600 700 800 900 1000 1100
Time[s]
Signals/Events State SLEEP
XOSC
XOSC delivers clock
CLKM delivers clock
Clock stable TRX_OFF PLL_ON
16 s PLL
IRQ PLL locked RX_ON
Active Blocks Command Pin
Timer 128 s
Timer 256 s
FTN BG
DVREG
AVREG
Time[s]
SLP_TR=0 P_ON
XOSC Timer 128 s
RST=0
PLL_ON, RX_ON
RX_ON Typical block settling time, stays on Block active waiting for SPI commands
VDD on
CLKM_CTRL
TRX_OFF
Figure 4-2.
Wake-up Procedure from SLEEP Mode and P_ON Mode to RX_ON Mode (PLL locked)
Forcing PLL_ON mode or RX_ON mode initiates a ramp-up sequence of the analog voltage regulator followed by a 16 s timer. This timer makes sure that the analog 1.8V supply is stabilized before enabling PLL circuitry. RX_ON mode can be forced any time during PLL_ON mode regardless of the PLL lock signal. When the wake-up sequence is started from P_ON mode (VDD first applied to the IC) the state machine will stop after the 128 s timer to wait for a valid TRX_OFF command from the micro-controller. The default CLKM frequency value in P_ON mode is 1 MHz. At this rate, an SPI access requires approximately 38 s. The SPI programming in synchronous mode can be speeded up by setting the frequency of the clock output at pin CLKM in register 0x03 (TRX_CTRL_0) to the maximum value allowed. If a chip reset with RST = 0 is generated, the sequence starts with filter tuning (FTN) as indicated in Figure 4-2.
4.3.2.
Transition from PLL_ON via BUSY_TX to RX_ON
0 10 16 x x+32 Time[s]
State
PLL_ON PLL settling to Tx frequency
PA BUSY_TX ramp Timer 14 s
PLL
PLL_ON RX_ON PLL settling to Rx frequency
Active Blocks Command Pin SLP_TR=0 TX_ START
2 s
Transmitting frame
PLL
Timer 32 s
Time[s]
Typical block settling time, stays on Block active waiting for SPI commands
RX_ON
Figure 4-3.
Switching from TX to RX
The time scale in Figure 4-3 is relative to TX frame start.
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4.3.3.
State Transition Timing
The transition numbers correspond to Figure 4-1 and do not include SPI access time if not otherwise stated. See measurement setup in Figure 9-1.
No 1 Transition P_ON TRX_OFF Time [s] Comments (typical) 1880 Internal power-on reset, including 1000 s for controller access, depends on external block capacitor at VDEC1 (1 F nom) and crystal oscillator setup (CL = 10 pf) Depends on external block capacitor at VDEC1 (1 F nom) and crystal oscillator setup (CL = 10 pf) 35 cycles of 1 MHz clock assumed. Depends on external block capacitor at VDEC2 (1 F nom).
2 3 4 5 6 7 8 9 10 11 12 13
SLEEP TRX_OFF TRX_OFF PLL_ON TRX_OFF RX_ON PLL_ON RX_ON PLL_ON BUSY_TX All modes
RST = 0

TRX_OFF SLEEP PLL_ON TRX_OFF RX_ON TRX_OFF RX_ON PLL_ON BUSY_TX PLL_ON TRX_OFF
TRX_OFF
880 35 180 1 180 1 1 1 16 32 1
120
Asserting SLP_TR pin
Using TRX_CMD FORCE_TRX_OFF (see register 0x02), not valid for SLEEP mode
Depends on external block capacitor at VDEC1 (1 F nom), not valid for P_ON mode
Table 4-1.
State Transition Timing
The state transition timing is calculated based on the timing of the single blocks shown in Figure 4-2. The worst case values include maximum operating temperature, minimum supply voltage, and device parameter variations.
Block
XOSC DVREG AVREG PLL, initial PLL, RX TX PLL, TX RX
Time [s] (typical)
500 60 60 100 16 32
Time [s] (worst case)
1000 1000 1000 150
Comments
Depends on crystal Q factor and load capacitor. Depends on external block capacitor at VDEC1 (CB3 = 1 F nom., 10 F worst case). Depends on external block capacitor at VDEC2 (CB1 = 1 F nom., 10 F worst case).
Table 4-2.
Block Timing
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5. Extended Operating Modes
The AT86RF230 transceiver implements address filtering, automatic acknowledgement frame generation and automatic frame retransmission for peer-to-peer networks in compliance with the IEEE 802.15.4 standard. Automatic modes help to achieve low power consumption and low peak current: TX-ARET (transmit/auto-retry) and RX-AACK (receive/auto-acknowledge). A TX-ARET transaction consists of: * * * * * CSMA/CA Frame transmission (if the channel is available) and automatic CRC generation Reception of ACK frame (if required by frame type and ACK request) Retry of CSMA/CA if the channel is busy or an ACK is expected but not received Interrupt signaling at the end of the transaction, with exit code (success, channel busy, no ACK)
A RX-AACK frame reception consists of: * * * * Frame reception and automatic CRC check Address filtering Interrupt signaling that the frame was received (if it passes address filtering) Automatic ACK frame transmission (if the received frame passed the address filter and if an ACK is required by the frame type and ACK request)
A state diagram including these extended operating modes is shown in Figure 5-1.
5.1.
Peer-to-peer Network Support
The automatic modes of the AT86RF230 are designed for peer-to-peer networks and non-slotted operation, as defined in the IEEE 802.15.4 standard. Note that automatic CRC generation can only be applied in conjunction with the TX-ARET mode, and automatic CRC check will only be applied in RX-AACK mode. In RX-AACK mode, an ACK frame will always be sent with the data-pending bit set to zero. In TX-ARET mode, an ACK is considered to be valid if the CRC is valid, and if the sequence number of the ACK corresponds to the previously transmitted frame. The value of the "data-pending" bit is ignored. Important Note: ACK frames will not be automatically generated for frames with either the broadcast PAN ID (0xFFFF) or a broadcast address.
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P_ON
(Power-on after VDD)
XOSC=ON Pull=ON
SLEEP
(Sleep Mode)
XOSC=OFF Pull=OFF
SL P_ TR SL =0 P_ TR =1
3
F OF X_ TR
1
2
FORCE_TRX_OFF
12
TRX_OFF
(Clock Mode)
XOSC=ON Pull=OFF
13
RST=0
(all modes except SLEEP)
(all modes except P_ON)
ON L_ PL
N
RX _O
7
TR X_ OF F
5
F OF X_ TR
6 Frame Start Frame End
TR P_ =1
4 Frame End 10 TX_START SLP_TR=1
BUSY_RX
(Receive Mode)
CLKM=ON
RX_ON
(Rx Listen Mode)
CLKM=ON
8
RX_ON PLL_ON
PLL_ON
(PLL Mode) 9
11
BUSY_TX
(Transmit Mode)
SL P_ TR
SL
RX_AACK_ON
PL L_ ON RX _A AC K_ ON
Frame Start
_ RX ON
RE _A TX
=0
RX_ON_NOCLK
(Rx Listen Mode)
CLKM=OFF
From TRX_OFF
TX_ARET_ON
PLL_ON
O T_ N
RX_ON
From TRX_OFF
BUSY_RX_AACK
(Auto Acknowledge)
Frame Start Transaction Finished
RX_AACK_ON
(Auto Acknowledge)
RX_AACK_ON TX_ARET_ON
TX_ARET_ON
(Auto Retry) Frame End
TX _A RE T_ ON
BUSY_RX_ AACK_NOCLK
Frame Start
(Auto Acknowledge) Frame (Auto Acknowledge) Rejected
RX_AACK_ ON_NOCLK
SLP_TR=0
SLP_TR=1
_ RX E AR ON T_
TX_START SLP_TR=1
BUSY_TX_ARET
(Auto Retry)
Frame Accepted
Legend: Blue: SPI Write to Register TRX_STATE (0x02) Red: Control signals via IC Pin Green: Event
Figure 5-1.
Extended Operating Mode State Diagram
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5.2.
Configuration
The initialization of the AT86RF230 prior to using RX-AACK or the TX-ARET mode is similar to initializing the IC prior to switching to regular RX or TX modes. RX_AACK_ON mode is enabled after the register bits TRX_CMD in register 0x02 (TRX_STATE) is written using RX_AACK_ON. The IC is in the RX_AACK_ON mode when the register 0x01 (TRX_STATUS) changes to RX_AACK_ON or BUSY_RX_AACK. For correct RX_AACK_ON operation, the register bit TX_AUTO_CRC_ON (register 0x05) must be set to "1". Similarly, TX_ARET_ON mode is enabled after the register bits TRX_CMD is written with TX_ARET_ON. The IC is in the TX_ARET_ON mode after TRX_STATUS changes to TX_ARET_ON or to BUSY_TX_ARET. For correct TXARET operation, the register bit TX_AUTO_CRC_ON (register 0x05) must be set to "1". The CSMA/CA algorithm can be configured using the 0x2D (CSMA_SEED_0) and the 0x2E (CSMA_SEED_1) registers. The MIN_BE register bits sets the minimum back-off exponent (refer to the IEEE 802.15.4 standard), and the CSMA_SEED_* register bits define a random seed for the back-off-time random-number generator in the AT86RF230. The register bits MAX_CSMA_RETRIES (register 0x2C) configures how often the transceiver will retry the CSMA/CA algorithm after a busy channel is initially detected. Both automatic modes can be exited by writing a new mode command to the register bits TRX_CMD in register 0x02 (TRX_STATE). Polling the 0x01 (TRX_STATUS) register for the new state confirms that the transceiver has left the automatic mode.
5.3.
5.3.1.
Extended Operation Mode Description
RX_AACK_ON
In the RX_AACK_ON mode, the transceiver listens for incoming frames. After detecting a frame start, the transceiver will parse the frame contents for frame type and destination address. The filtering procedure described in IEEE 802.15.4 will be applied to the frame. Any frames rejected by address filtering will be discarded. A frame will also be discarded if the CRC is found to be invalid. Otherwise, the TRX_END interrupt will be raised after the reception of the frame is completed. The controller can then upload the frame. The transceiver also detects if an ACK frame needs to be sent. If this is true, the transceiver will automatically send an ACK frame 12 symbol periods after the end of the received frame. Only ACKs with a cleared data-pending bit will be transmitted. No ACK will be sent if no ACK is required.
5.3.2.
TX_ARET_ON
In TX_ARET_ON mode, the transceiver executes the CSMA/CA algorithm and transmits a frame downloaded by the controller. If necessary, it will check for an ACK reply, and signal the result of the transaction by raising a TRX_END interrupt. After the interrupt, the controller may read the value of the register bits TRAC_STATUS (register 0x02) to determine whether or not the transaction was successful. The CSMA/CA transmission transaction is started by pulsing the SLP_TR pin high for at least one microsecond. The frame data must have already been downloaded. Alternatively, the controller may download the frame data while the transceiver is transmitting the preamble. In this case, it is the responsibility of the controller to ensure that the data arrives sufficiently early. The transceiver executes the un-slotted CSMA/CA algorithm as defined by the IEEE 802.15.4 standard. If a clear channel is detected during CSMA/CA execution, the transceiver will proceed to transmit the frame. If the CSMA/CA did not detect a clear channel, the channel access will be retried as often as set by the register bits MAX_CSMA_RETRIES in register 0x2C (XAH_CTRL). In case that CSMA/CA does not detect a clear channel
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even after the maximum number of retries, it will abort the transaction, raise the TRX_END interrupt, and set the value of the TRAC_STATUS register bits to CHANNEL_ACCESS_FAILURE. Upon the detection of a clear channel, the transceiver starts the frame transmission. It parses the frame as it is transmitted to check if an ACK reply will be expected. If no ACK is expected, the transceiver will raise an interrupt after the frame transmission completes. The value of register bits TRAC_STATUS (register 0x02) is set to SUCCESS. On the other hand, if the transmitted frame requires an ACK, the transceiver switches into receive mode to wait for a valid ACK reply. If no valid ACK is received, the transceiver will retry the entire transaction, including CSMA/CA execution, until the frame has been acknowledged or the maximum number of retransmissions (as set by the register bits MAX_FRAME_RETRIES in register 0x2C) has been reached. In this case, the TRX_END interrupt is raised and the value of TRAC_STATUS is set to NO_ACK. If a valid ACK is found, the TRX_END interrupt will be raised. In this case, TRAC_STATUS is set to SUCCESS.
5.3.3.
RX_AACK_NOCLK
If the radio is listening for an incoming frame and the controller is not running an application, the controller can be powered down to decrease the total system power consumption. This special power down scenario (similar to RX_ON_NOCLK) for controllers running in synchronous mode is supported by the AT86RF230 using the state RX_AACK_NOCLK. The state can only be entered by setting SLP_TR = 1 while the IC is in the RX_AACK_ON mode. The CLKM pin will be disabled 35 clock cycles after the rising edge at the SLP_TR pin. This will enable the controller to complete its power down sequence. In RX_AACK_NOCLK mode, the transceiver listens for IEEE 802.15.4 frames. Should the AT86RF230 detect an Start-of-Frame-Delimiter, it will enter the BUSY_RX_AACK_NOCLK state, and it will start to receive the frame. If the frame passes the address filter, the AT86RF230 enters the BUSY_RX_AACK state, and the clock supplied to the micro-controller is turned back on. The controller may now process the incoming frame. If the received frame has a valid CRC, and if it requires an acknowledgement, the transceiver will automatically generate and transmit an ACK frame. The end of the transaction is signaled to the controller by an TRX_END interrupt. After the transaction has been completed, the transceiver will enter the RX_AACK_ON state. The transceiver will only re-enter the RX_AACK_NOCLK state when the SLP_TR has been reset to "0", and afterwards set to "1" again. If the transceiver is in the RX_AACK_NOCLK state, and the SLP_TR pin is reset to "0", it will enter the RX_AACK_ON state, and it will again start to supply the micro-controller with the clock signal.
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6. Functional Description
6.1. RSSI/Energy Detection
The internal limiter amplifier provides an RSSI value which reflects the current receive signal strength at the antenna pin of the AT86RF230. The RSSI is a 5-bit value indicating the receive power in steps of 3 dB (see register 0x06), and is updated every 2 s. The receiver ED measurement is used with the channel-scan algorithm. An ED request (write access to register 0x07) as defined by the IEEE 802.15.4 standard has a measurement time of 128 s. The ED measurement result is accessible after the measurement time at register 0x07 (PHY_ED_LEVEL). With every frame reception (SFD detection), an ED measurement is automatically started. The ED measurement result has the same range as the RSSI value (register 0x06), but with a 1 dB resolution.
6.2.
Link Quality Indication
The IEEE 802.15.4 standard defines the link quality indication (LQI) measurement as a "characterization of the strength and/or quality of a received packet". The LQI measurement of the AT86RF230 is implemented as a characterization of both the quality and signal strength. An average correlation value of multiple symbols is calculated and appended to each frame after scaling to a value ranging from 0 to 255. The minimum LQI value of 0 is associated with a low signal quality, resulting from high signal distortions, and/or a signal strength that is below the receiver sensitivity. The maximum value of 255 is associated with a signal strength higher than the receiver sensitivity and a high signal quality resulting from low signal distortions. Signal distortions are mainly generated by interference and multipath propagation.
6.3.
* * *
Clear Channel Assessment
Mode 1: energy above threshold only Mode 2: carrier sense only Mode 3: carrier sense with energy above threshold
The IEEE 802.15.4 standard defines three clear channel assessment (CCA) modes:
All three modes are available in AT86RF230. The modes are configurable via register 0x08 (PHY_CC_CCA). A CCA request is initiated by writing to bit 7 in register 0x08 (PHY_CC_CCA). After the CCA evaluation time of 128 s, the CCA result is accessible at register 0x01 (TRX_STATUS) bits 6 and 7. Bit 7 indicates whether the CCA measurement is finished or not, bit 6 indicates a busy (bit 6 = 0) or clear channel. (bit 6 = 1) The CCA modes are further configurable using register 0x09 (CCA_THRES). The 4-bit value CCA_CS_THRES can be used for fine tuning the sensitivity of the CCA carrier sense algorithm. Higher values increase the probability of clear channel detection. The other 4-bit value (CCA_ED_THRES) of register 0x09 (CCA_THRES) defines the received power threshold of the "energy above threshold" algorithm. Any received power above this level will indicate a busy channel. The threshold is calculated by -91+2*CCA_ED_THRES [dBm], resulting in a range of -91 dBm to -61 dBm.
6.4.
Voltage Regulators
Two identical low-dropout voltage regulators are integrated within the AT86RF230. The AVREG provides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the low-voltage digital section. A simplified schematic is shown in Figure 6-1. The voltage regulators are connected internally to the external unregulated supply voltage VDD. The regulated output voltage is available on pin VDEC1 or VDEC2. External decoupling capacitors should be connected to these pins to stabilize the regulated supply voltage. A decoupling capacitor value of 1 F is recommended for stable operation of the voltage regulators (see chapter 9), but it can
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range from 400 nF to 10 F. A higher capacitor value provides better voltage stability, but increases the voltage regulator settling time.
VDD
Bandgap voltage reference
1.25V
VDEC VREG_TRIM[1:0]
Figure 6-1.
Simplified Schematic of VREG
The voltage regulators can be configured using the register 0x10 (VREG_CTRL). The read-only bit values AVDD_OK = 1 and DVDD_OK = 1 indicate a stable, regulated supply voltage. It is possible to use external voltage regulators instead of the internal regulators. For this special application the internal regulators need to be switched off by setting the register bits to the values AVREG_EXT = 1 and DVREG_EXT = 1. A regulated external supply voltage of 1.8V needs to be connected to the pins VDEC1 and VDEC2. When turning on the external supply, ensure a sufficiently long stabilization time before interacting with the AT86RF230.
6.5.
Battery Monitor
The battery monitor (BATMON) detects and signals a low battery or supply voltage. This is done by comparing the current voltage on the VDD pins with a programmable internal threshold voltage. Figure 6-2 shows the simplified schematic of the BATMON with the most important input and output signals.
BATMON_HR 4 BATMON_VTH
DAC
VDD
+
BATMON_OK
Threshold Voltage
-
1"
clear D Q
For input-to-output mapping see control register 0x11 (BATMON)
BATMON_IRQ
Figure 6-2. Simplified Schematic of BATMON
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The BATMON can be configured using the register 0x11 (BATMON). BATMON_VTH[3:0] sets the threshold voltage. It is programmable with a resolution of 75 mV in the upper voltage range (BATMON_HR = 1) and with a resolution of 50 mV in the lower voltage range (BATMON_HR = 0). The signal-bit BATMON_OK indicates the current value of the battery voltage: * * If BATMON_OK is "0", the battery voltage is lower than the threshold voltage If BATMON_OK is "1", the battery voltage is higher than the threshold voltage
Furthermore, an interrupt (IRQ7) is automatically generated when the battery voltage falls below the programmed threshold (see control register 0x0F and 0x0E). The interrupt appears only when BATMON_OK changes from "1" to "0". No interrupt will be generated when: * * the battery voltage is under the default 1.8V threshold at power up (BATMON_OK was never "1"), or a new threshold is set, which is above the current battery voltage (BATMON_OK remains "0").
After setting a new threshold, the value BATMON_OK should be read out to verify the current supply voltage value. When the battery voltage is close to the programmed threshold voltage, noise or temporary voltage drops can generate a lot of unwanted interrupts initiated by a toggling BATMON_OK signal. To avoid this: * * disable the IRQ7-bit in IRQ mask register after the first interrupt and treat the battery as empty, or set a lower threshold value after the first interrupt.
Note that the battery monitor is inactive during PON and SLEEP modes, see control register 0x01 (TRX_STATUS).
6.6.
Crystal Oscillator
The crystal oscillator generates the reference frequency for the AT86RF230. All other internally-generated frequencies in the transceiver are derived from this unique frequency. Therefore the overall system performance is mainly based on the accuracy of this reference frequency. The external components of the crystal oscillator should be selected carefully and the related board layout should be done meticulously. The register 0x12 (XOSC_CTRL) provides access to the control signals of the oscillator. Basically, two operating modes are supported. A reference frequency can be fed to the internal circuitry by using an external clock reference or by setting up the integrated oscillator as described in Figure 6-3. Using the internal oscillator, the oscillation frequency strongly depends on the load capacitance seen by the crystal between the crystal pins XTAL1 and XTAL2. The total load capacitance must be equal to the specified load capacitance CL of the crystal itself. It consists of the external capacitors CX and parasitic capacitances connected to the XTAL nodes. In Figure 6-3, all parasitic capacitances, such as PCB stray capacitances and the pin input capacitance, are summarized to CPAR. Additional internal trimming capacitors CTRIM are available. Any value in the range from 0 pF to 4.8 pF with a 0.3 pF resolution is selectable using the register bits XTAL_TRIM[3:0]. To calculate the total load capacitance, the following formula can be used CL = 0.5*(CX+CTRIM+CPAR). The trimming capacitors provide the possibility of an easy adjustment of frequency changes caused by production process variations or by tolerances of the external components. Note that the oscillation frequency can be reduced only by increasing the trimming capacitance. The frequency deviation caused by one unit of CTRIM decreases with increasing crystal load capacitor values. An amplitude control circuit is included to ensure stable operation with different operating conditions and different crystal types. A high current during the amplitude build-up phase guarantees a low start-up time. At stable operation, the current is reduced to the amount necessary for a robust operation. This also keeps the drive level of the crystal low. Generally, crystals with a higher load capacitance are less sensitive to parasitic pulling effects caused by external component variations or by variations of board and circuit parasitics. On the other hand, a larger crystal load capacitance results in a longer start-up time and a higher steady state current consumption.
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VDD
XTAL_TRIM[3:0] CTRIM
XTAL_TRIM[3:0] CTRIM
AT86RF230
XTAL2
16MHz
XTAL1
PCB
CPAR
CX
CX
CPAR
Figure 6-3.
Simplified XOSC Schematic with External Components
When using an external reference frequency, the signal needs to be connected to pin XTAL1 as indicated in Figure 6-4 and the register bits XTAL_MODE needs to be set to the external oscillator mode. The oscillation amplitude shouldn't be larger than 500 mV, peak-to-peak.
AT86RF230
XTAL2
XTAL1
PCB
16 MHz
Figure 6-4.
Setup for Using an External Frequency Reference
6.7.
PLL Frequency Synthesizer
The synthesizer of the AT86RF230 is implemented as a fractional-N PLL. Two calibration loops ensure correct functionality within the specified operating limits. The center frequency control loop ensures a correct center frequency of the VCO for the currently programmed channel. The center frequency calibration algorithm can be started manually by setting PLL_CF_START = 1 of register 0x1A (PLL_CF). The result of the calibration is also available in this register. The delay calibration unit compensates the phase errors inherent in fractional-N PLLs. Using this technique, unwanted spurious frequency components beside the RF carrier are suppressed, and the PLL behaves almost like an integer-N PLL. A calibration cycle can be initiated by setting the register bit PLL_DCU_START = 1 of the register 0x1B (PLL_DCU). The calibration result is written to the register bits PLL_DCUW.
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Both calibration routines will be initiated automatically when the PLL is turned on. Additionally, the center frequency calibration is running when the PLL is programmed to a different channel (register 0x08 bits [4:0]). If the PLL is not turned off for a long time, the control loops should be manually initiated from time to time. The calibration interval depends on environment temperature variations but should not be longer than 5 min.
6.8.
Automatic Filter Tuning
The filter-tuning unit is a separate building block within the AT86RF230. A calibration cycle is initiated automatically when entering the TRX_OFF state from either the SLEEP, RESET or P_ON states. The result of the calibration is the 6-bit word FTNV, and is written to the register 0x18 (FTN_CTRL). The filter-tuning value FTNV is used to provide a stable SSBF transfer function and PLL loop-filter time constant independent of temperature effects and part-to-part variations. It is possible to trigger the calibration algorithm manually by setting the register bit FTN_START = 1.
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7. PHY to Micro-Controller Interface
In the following paragraphs, the PHY to micro-controller interface is defined. The SPI protocol and timing access are shown, as well as buffer access modes with examples. Controllers with an SPI interface such as an AVR will work with the AT86RF230 interface. The SPI interface is used for both register programming as well as for frame transfer. The additional control signals are connected to the GPIO interface of the controller. Figure 7-1 shows the signals which need to be connected between the controller and the transceiver. The CLKM signal can be used as a controller main clock (synchronous mode) or as software timer reference (asynchronous mode).
Micro-Controller
SEL SEL
AT86RF230
SEL
MISO SCLK GPIO1/CLK GPIO2/IRQ GPIO3 GPIO4
Figure 7-1.
MISO SCLK CLKM IRQ SLP_TR
RST
MISO SCLK CLKM IRQ SLP_TR
RST
PHY-HOST Interface
7.1.
SPI Protocol
SPI is used to program control registers as well as to transfer data frames between the controller and the AT86RF230. The additional signals CLKM, IRQ, SLP_TR and RST are connected to the GPIO interface of the controller. The internal 128-byte frame buffer can keep one TX or one RX frame of maximum length at a time. This offers a very flexible data rate over the SPI interface.
SEL SCLK t1 MISO Bit7 t3 t4 MOSI Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 t7 SLP_TR t2 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 t5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 t6
Figure 7-2.
SPI Timing
SPI
MOSI
MOSI
MOSI
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The interface is designed to work in synchronous or asynchronous mode. In synchronous mode, the CLKM output of the transceiver IC is used as the master clock of the controller. The SPI clock can be any integer-divided clock ratio up to 8 MHz. Nevertheless, usage of an independent controller clock for an asynchronous interface is possible. In asynchronous mode, the maximum SPI clock speed is limited to 7.5 MHz. The external CLKM output signal is not required and can be disabled.
SEL enables the MISO output driver of the AT86RF230. If the driver is disabled, there is no internal pull-up resistor connected to it. Driving the appropriate signal level must be ensured by the master device or an external pull-up resistor.
The SPI is a byte-oriented serial interface. All bytes are transferred MSB first. Every SPI transfer starts with SEL = 0 and this signal is asserted low as long as one consecutive SPI access occurs. One consecutive access includes two or more bytes depending on the access mode described later. If SEL = 0 goes high before the end of one complete access, the internal bit counter is reset and the transferred data are lost. Both sides of the interface (master and slave) contain an 8-bit shift register. The master starts the transfer by asserting SEL = 0 . After the 8-bit shift register is loaded, the master generates eight SPI clocks in order to transfer the data to the slave, and at the same time the slave transmits one byte to the master shift register. If the master wants to receive one byte of data it must also transmit one byte to the slave. Every transfer starts with a command byte. This command byte contains the access mode information as well as additional mode-dependent bits. During command byte transfer, the AT86RF230 returns a byte containing "0".
Bit 7
1 1 0 0 0 0
Bit 6 (R/W)
0 1 0 1 0 1
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mode
Short mode (register read access) Short mode (register write access) Frame receive mode Frame transmit mode SRAM read access mode SRAM write access mode
Register address [5:0] Register address [5:0] 1 1 0 0 Reserved Reserved Reserved Reserved
Table 7-1.
Interface Access Mode Overview
7.2.
Register Access Mode (Short Mode)
The register access mode is a two-byte read/write operation. The first byte contains the control information (mode identifier bit 7, read/write select bit 6, and a 6-bit address). The second byte contains the read or write data. In this mode a maximum of 64 consecutive registers can be addressed.
1 R/W
1=write 0=read
address[5:0] byte 1
data[7:0] byte 2
Figure 7-3.
Register Short Mode Access
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Write Register Access
Read Register Access
CLKM SEL SCLK MOSI MISO
COMMAND XX WRITE DATA XX COMMAND XX XX READ DATA
Figure 7-4.
SPI Register Access Sequence
7.3.
Frame Buffer Access Modes (Long Modes)
These modes are used to upload or download frames as well as access the frame buffer directly. Each transfer starts with a control byte. If this byte indicates a frame upload or download, the next byte indicates the frame length followed by the PSDU data. In receive mode, after the PSDU data has been received, one more byte is attached, containing LQI information. The number of bytes for one frame access must be calculated by the controller as follows: Transmit: Receive: byte_count = command byte + frame length byte + frame length byte_count = command byte + frame length byte + frame length + LQI byte
That means there is a maximum frame buffer access of 129 bytes for TX and 130 bytes for RX.
0
TX/RX
0
1 byte 1
control[4:0]
(reserved)
frame_length[7:0] byte 2
data[7:0] byte 3
data[7:0] byte n-1
LQI[7:0] byte n
Figure 7-5.
TX/RX
Frame Receive Mode
0
1
1 byte 1
control[4:0]
(reserved)
frame_length[7:0] byte 2
data[7:0] byte 3
data[7:0] byte n
Figure 7-6.
Frame Transmit Mode
If the control byte indicates SRAM access mode, the next byte contains the start address. As long as SEL is low, every subsequent byte read or write increments the address counter of the frame buffer.
0 R/W
1=write 0=read
0 byte 1
control[4:0]
(reserved)
address[7:0] byte 2
data[7:0] byte 3
data[7:0] byte n
Figure 7-7.
SRAM Access Mode
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7.4.
Frame Receive Procedure
IRQ issued read IRQ status register (register access)
The following transactions are required to receive a frame over the SPI:
IRQ line deasserted receiving frame data (frame receive mode)
Figure 7-8.
Receive Frame Transactions Between AT86RF230 and Controller
CLKM IRQ_status_read SEL SCLK MOSI MISO IRQ SLP_TR
COMMAND
Frame_upload
XX
READ DATA
COMMAND
XX
XX
XX
XX
Controller
XX
PHY
XX
LQI Value
XX IRQ issued
XX
FRAME LENGTH FRAME DATA 1 FRAME DATA 2 FRAME DATA 3 FRAME DATA n
Figure 7-9.
Frame Receive Sequence
7.5.
Frame Transmit Procedure
The following transactions are required to transmit a frame over SPI:
write frame data to transceiver (frame transmit mode)
write tx_start bit to register (register access) or assert SLP_TR (depends on configuration)
Figure 7-10.
Transmit Frame Transactions Between AT86RF230 and Controller
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Controller
PHY
AT86RF230
CLKM Frame_download SEL SCLK MOSI MISO IRQ SLP_TR Transmit Start COMMAND XX
FRAME LENGTH FRAME DATA 1 FRAME DATA 2 FRAME DATA 3 FRAME DATA n
XX
XX
XX
XX
XX
Figure 7-11.
Frame Transmit Sequence (SLP_TR Assertion Starts Transmission)
7.6.
Sleep/Wake-up and Transmit Signal
The SLP_TR signal is a multi-functional pin. It can be used as transmit start or as a sleep signal. The function of the pin depends on the transceiver status.
Transceiver Status
TRX_OFF RX_ON PLL_ON TX_ARET_ON RX_AACK_ON
Pin Function
Sleep Disable CLKM TX start TX start TX start
Description
Forces the transceiver into SLEEP mode Forces the transceiver into RX_ON_NOCLOCK state and disables CLKM Start frame transmission Start of frame retry Start of frame acknowledge
Table 7-2.
SLP_TR Multi-functional Pin States
The pin has no function if the transceiver is in other modes. If used as a sleep signal, releasing the pin SLP_TR = 0 forces the transceiver into TRX_OFF mode and enables the main clock. If used as a transmit start signal, the low-to-high edge starts the transmission of a frame stored in the frame buffer. From the application point of view, there are two possible power-down scenarios supported by the AT86RF230. Either both the controller and the AT86RF230 are powered down, or the AT86RF230 listens for an incoming frame and only the controller is powered down. The first power-down scenario is shown in Figure 7-12. The controller forces the AT86RF230 to SLEEP mode by setting SLP_TR to "1" when the transceiver is in TRX_OFF mode. The main clock at pin CLKM will be switched off after 35 clock cycles. This enables the controller to complete its power-down routine and prevent dead-lock situations. The AT86RF230 will awaken when the controller releases the pin SLP_TR. This concept provides the lowest possible power consumption. If an incoming frame is expected and no other application is running on the controller, the controller itself can be powered down without the risk of missing an incoming frame. This scenario is shown in Figure 7-13. In RX_ON state, the CLKM pin will switched off after 35 clock cycles when the pin SLP_TR is set to "1". The start of a frame reception will be signaled by an RX_START IRQ and the clock will be switched on again.
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5131A-ZIGB-06/14/06
CLKM
async timer (controller) elapsed 35 main clock cycles
SLP_TR
Figure 7-12.
CLKM
Sleep and Wake-up Initiated by Asynchronous Controller Timer Output
35 main clock cycles
SLP_TR
transceiver IRQ issued
IRQ
Figure 7-13.
Wake-up Initiated by Transceiver Interrupt
7.7.
Interrupt Logic
The AT86RF230 can differentiate between six interrupt events. Each interrupt can be enabled or disabled by writing the corresponding bit to the interrupt mask register. All six internal interrupt lines are combined via logical "OR" to one external interrupt line. Internally, each interrupt is stored in a separate bit of the interrupt status register. If the external interrupt line is set, the controller must first read the interrupt status register to determine the source of the interrupt. A read access to this register clears the interrupt status register and also the external interrupt line. The interrupt will not be cleared automatically when the event that caused the IRQ is not valid anymore. Exception: the PLL_LOCK IRQ will clear the PLL_UNLOCK IRQ and vice versa. For a detailed description of the interrupt status register, please refer to register 0x0F (IRQ_STATUS). Note: After a reset signal, all interrupts are enabled. Special settings in the register 0x0E (IRQ_MASK) need to be renewed.
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8. Control Registers
The AT86RF230 provides a register space of 64 8-bit registers, which is used to configure the IC as well as to store signaling information read by the firmware. Note that all registers not mentioned within the following table are reserved for internal use and must not be written to. When writing to a non-reserved register, any individual bits of that register marked as reserved can only be overwritten by their reset value.
Reg.-Addr.
0x01 0x02 0x03 0x05 0x06 0x07 0x08 0x09 0x0E 0x0F 0x10 0x11 0x12 0x18 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28
Register Name
TRX_STATUS TRX_STATE TRX_CTRL_0 PHY_TX_PWR PHY_RSSI PHY_ED_LEVEL PHY_CC_CCA CCA_THRES IRQ_MASK IRQ_STATUS VREG_CTRL BATMON XOSC_CTRL FTN_CTRL PLL_CF PLL_DCU PART_NUM VERSION_NUM MAN_ID_0 MAN_ID_1 SHORT_ADDR_0 SHORT_ADDR_1 PAN_ID_0 PAN_ID_1 IEEE_ADDR_0 IEEE_ADDR_1 IEEE_ADDR_2 IEEE_ADDR_3 IEEE_ADDR_4
Description
Transceiver status, CCA result State/mode control Driver current and controller clock setting TX power setting RSSI value RX energy level CCA mode configuration, CCA request, channel setting CCA_ED and CCA_CS threshold Interrupt mask Interrupt status Voltage regulator control Battery monitor control Crystal oscillator control Filter tuning control PLL center frequency calibration PLL delay calibration Part ID Version ID Manufacturer ID, lower 8 bits Manufacturer ID, higher 8 bits Short address for address recognition Short address for address recognition PAN address for address recognition PAN address for address recognition Current node IEEE address for address recognition Current node IEEE address for address recognition Current node IEEE address for address recognition Current node IEEE address for address recognition Current node IEEE address for address recognition
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Reg.-Addr.
0x29 0x2A 0x2B 0x2C 0x2D 0x2E
Register Name
IEEE_ADDR_5 IEEE_ADDR_6 IEEE_ADDR_7 XAH_CTRL CSMA_SEED_0 CSMA_SEED_1
Description
Current node IEEE address for address recognition Current node IEEE address for address recognition Current node IEEE address for address recognition Retries value control CSMA seed value CSMA seed value
Table 8-1.
Bit
7 6
Configuration registers overview
Reset
0 0
Field Name
CCA_DONE CCA_STATUS
R/W
R R
Comments
1'd0: 1'd1: CCA calculation in progress CCA calculation done
Indicates an idle channel from CCA module. CHANNEL_IDLE: 1'd0: channel is busy 1'd1: channel is idle Reserved Signals the current transceiver status. TRANSCEIVER_STATUS: 5'd0: P_ON 5'd1: BUSY_RX 5'd2: BUSY_TX 5'd6: RX_ON 5'd8: TRX_OFF (CLK Mode) 5'd9: PLL_ON (TX_ON) 5'd15: SLEEP 5'd17: BUSY_RX_AACK 5'd18: BUSY_TX_ARET 5'd22: RX_AACK_ON 5'd25: TX_ARET_ON 5'd28: RX_ON_NOCLK 5'd29: RX_AACK_ON_NOCLK 5'd30: BUSY_RX_AACK_NOCLK 5'd31: state transition
5 4:0 TRX_STATUS
0 0
R R
Table 8-2. Note:
0x01 - TRX_STATUS A register read will reset the CCA_STATUS bit and the CCA_DONE bit if a CCA calculation was done (CCA_DONE = 1).
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Bit
7:5
Field Name
TRAC_STATUS
Reset
0
R/W
R
Comments
3'd0: SUCCESS 3'd3: CHANNEL_ACCESS_FAILURE 3'd5: NO_ACK All other values are reserved. Transceiver control commands: 5'd0: NOP 5'd2: TX_START 5'd3: FORCE_TRX_OFF 5'd6: RX_ON 5'd8: TRX_OFF (CLK Mode) 5'd9: PLL_ON (TX_ON) 5'd22: RX_AACK_ON 5'd25: TX_ARET_ON All other values are mapped to NOP.
4:0
TRX_CMD
0
R/W
Table 8-3. Note:
0x02 - TRX_STATE TRX_CMD = "0" after power on reset (POR). Frame transmission starts 16 s after TX_START command.
Bit
7:6
Field Name
PAD_IO
Reset
0
R/W
R/W
Comments
Set the output driver current of digital pads (except CLKM pad). 2'd0: 2 mA 2'd1: 4 mA 2'd2: 6 mA 2'd3: 8 mA Set the output driver current of CLKM. 2'd0: 2 mA 2'd1: 4 mA 2'd2: 6 mA 2'd3: 8 mA Shadow the CLKM_CTRL clock changes. If the mode is enabled, changes to the CLKM_CTRL bits take effect only when the IC leaves the SLEEP mode. 1'd0: disable (on the fly) 1'd1: enable (shadow) Controls the clock frequency at the CLKM pad. 3'd0: no clock 3'd1: 1 MHz 3'd2: 2 MHz 3'd3: 4 MHz 3'd4: 8 MHz 3'd5: 16 MHz 3'd6: no clock 3'd7: no clock
5:4
PAD_IO_CLKM
1
R/W
3
CLKM_SHA_SEL
1
R/W
2:0
CLKM_CTRL
1
R/W
Table 8-4.
0x03 - TRX_CTRL_0
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5131A-ZIGB-06/14/06
Bit
7
Field Name
TX_AUTO_CRC_ON
Reset
0
R/W
R/W
Comments
AUTO_CRC mode: 1'd0: disable 1'd1: enable Reserved
6:4 3:0 TX_PWR
0 0
R R/W
TX Power Mapping
TX Power Setting 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Output Power [dBm] 3.0 2.6 2.1 1.6 1.1 0.5 -0.2 -1.2 -2.2 -3.2 -4.2 -5.2 -7.2 -9.2 -12.2 -17.2
Table 8-5.
Bit
7:5 4:0 RSSI
0x05 - PHY_TX_PWR
Reset
0 0
Field Name
R/W
R R
Comments
Reserved 5'd0: RX input level < -91 dBm 5'd27: RX input level > -10 dBm RSSI is a linear curve on a logarithmic input power scale (dBm) with a 3 dB step width.
Table 8-6.
0x06 - PHY_RSSI
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Bit
7:0
Field Name
ED_LEVEL
Reset
0
R/W
R
Comments
ED level for current channel. The min. ED value (0) indicates receiver power less than or equal to -91 dBm. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of 5 dB.
Table 8-7. Note:
Bit
7 6:5
0x07 - PHY_ED_LEVEL A write access initiates the ED measurement (ED.request).
Field Name
CCA_REQUEST CCA_MODE
Reset
0 1
R/W
R/W R/W
Comments
1'd1: starts a CCA check (CCA.request) read value always returns with "0" CCA Mode: 2'd0: Mode 1, energy above threshold 2'd1: Mode 1, energy above threshold 2'd2: Mode 2, carrier sense only 2'd3: Mode 3, carrier sense with energy above threshold Channel: According to IEEE802.15.4 only 11 to 26 are valid. All unused values are reserved.
4:0
CHANNEL
11
R/W
Channel Mapping
Channel Number 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Frequency [MHz] 2405 2410 2415 2420 2425 2430 2435 2440 2445 2450 2455 2460 2465 2470 2475 2480
Table 8-8.
0x08 - PHY_CC_CCA
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5131A-ZIGB-06/14/06
Bit
7:4 3:0
Field Name
CCA_CS_THRES CCA_ED_THRES
Reset
12 7
R/W
R/W R/W
Comments
Threshold for CCA_CS An ED value above the threshold signals a busy channel during a CCA_ED measurement.
Table 8-9. Note:
0x09 - CCA_THRES CCA_ED_THRES: The CCA_ED request will indicate a busy channel, if the measured receive power is above -91 dBm + 2*CCA_ED_THRES[dB].
Bit
7:0
Field Name
IRQ_MASK
Reset
255
R/W
R/W
Comments
Mask register for IRQs. If bit is set to high, then the IRQ is enabled. If bit is set to low, then the IRQ is disabled. IRQ_MASK[7] corresponds to IRQ_7. IRQ_MASK[0] corresponds to IRQ_0.
Table 8-10. Note:
Bit
7 6 5 4 3 2 1 0
0x0E - IRQ_MASK The occurrence of an interrupt will be signaled over the IRQ wire.
Field Name
IRQ_7 IRQ_6 IRQ_5 IRQ_4 IRQ_3 IRQ_2 IRQ_1 IRQ_0
Reset
0 0 0 0 0 0 0 0
R/W
R R R R R R R R
Comments
BAT_LOW: TRX_UR: Reserved Reserved TRX_END: RX_START: PLL_UNLOCK: PLL_LOCK: signals end of frame (transmit and receive) signals beginning of receive frame PLL goes from lock to unlock state PLL goes from unlock to lock state signals low battery signals a FIFO underrun
Table 8-11. Note:
0x0F - IRQ_STATUS The occurrence of an interrupt will be signaled over the IRQ wire. A read access will reset the interrupt bits.
Bit
7 6 5:4
Field Name
AVREG_EXT AVDD_OK AVREG_TRIM
Reset
0 0 0
R/W
R/W R R/W
Comments
1'd0: 1'd1: 1'd0: 1'd1: use internal analog voltage regulator use external voltage regulator analog voltage regulator is disabled internal analog voltage is correct and stable
Controls the voltage of the analog voltage regulator. 2'd0: 1.80V 2'd1: 1.75V 2'd2: 1.84V 2'd3: 1.88V
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Bit
3 2 1:0
Field Name
DVREG_EXT DVDD_OK DVREG_TRIM
Reset
0 0 0
R/W
R/W R R/W
Comments
1'd0: 1'd1: 1'd0: 1'd1: use internal digital voltage regulator use external voltage regulator digital voltage regulator is disabled internal digital voltage is correct and stable
Controls the voltage of the digital voltage regulator. 2'd0: 1.80V 2'd1: 1.75V 2'd2: 1.84V 2'd3: 1.88V
Table 8-12.
Bit
7:6 5
0x10 - VREG_CTRL
Reset
0
Field Name
R/W
R R
Comments
Reserved Result of battery monitor: 1'd0: not valid (VDD < BATMON_VTH) 1'd1: valid (VDD > BATMON_VTH) High range switch (mapping see BATMON_VTH) Threshold voltage:
BATMON_OK
0
4 3:0
BATMON_HR BATMON_VTH
0 2
R/W R/W
BATMON_VTH Mapping
Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Voltage [V] BATMON_HR = "1" 2.550 2.625 2.700 2.775 2.850 2.925 3.000 3.075 3.150 3.225 3.300 3.375 3.450 3.525 3.600 3.675 Voltage [V] BATMON_HR = "0" 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45
Table 8-13.
0x11 - BATMON
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5131A-ZIGB-06/14/06
Bit
7:4
Field Name
XTAL_MODE
Reset
15
R/W
R/W
Comments
XTAL Modes: 4'd0: switch off 4'd4: external oscillator 4'd15: internal oscillator All other modes are reserved and should not be used. Binary coded capacitance array for XTAL trimming. Values: 0 pF, 0.3 pF, ..., 4.8 pF
3:0
XTAL_TRIM
0
R/W
Table 8-14.
Bit
7 6 5:0 FTNV
0x12 - XOSC_CTRL
Reset
0 1 24
Field Name
FTN_START
R/W
R/W R/W R/W
Comments
1'd1: Initiates filter calibration cycle If filter calibration is finished, read value is "0" Reserved Filter tuning value
Table 8-15.
Bit
7 6:4 3:0 PLL_CF
0x18 - FTN_CTRL
Reset
0 5 15
Field Name
PLL_CF_START
R/W
R/W R/W R/W
Comments
1'd1: Initiates PLL center frequency calibration cycle If frequency calibration is finished, read value is "0" Reserved VCO center frequency control word
Table 8-16.
Bit
7 6 5:0
0x1A - PLL_CF
Reset
0 0
Field Name
PLL_DCU_START
R/W
R/W R R/W
Comments
1'd1: Initiates PLL delay cell calibration cycle If delay cell calibration is finished, read value is "0" Reserved Delay cell control word
PLL_DCUW
32
Table 8-17.
Bit
7:0
0x1B - PLL_DCU
Reset
2
Field Name
PART_NUM
R/W
R
Comments
The device part number. 8'd2: AT86RF230 All other values are reserved
Table 8-18.
Bit
7:0
0x1C - PART_NUM
Reset
1
Field Name
VERSION_NUM
R/W
R
Comments
The device version number.
Table 8-19.
0x1D - VERSION_NUM
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Bit
7:0
Field Name
MAN_ID_0
Reset
31
R/W
R
Comments
JEDEC manufacturer ID is 32'h 00_00_00_1F for Atmel, bits[7:0]
Table 8-20.
Bit
7:0
0x1E - MAN_ID_0
Reset
0
Field Name
MAN_ID_1
R/W
R
Comments
JEDEC manufacturer ID is 32'h 00_00_00_1F for Atmel, bits[15:8]
Table 8-21.
Bit
7:0
0x1F - MAN_ID_1
Reset
0
Field Name
SHORT_ADDR_0
R/W
R/W
Comments
Lower 8 bits of short address for address recognition, bits[7:0]
Table 8-22.
Bit
7:0
0x20 - SHORT_ADDR_0
Reset
0
Field Name
SHORT_ADDR_1
R/W
R/W
Comments
Higher 8 bits of short address for address recognition, bits[15:8]
Table 8-23.
Bit
7:0
0x21 - SHORT_ADDR_1
Reset
0
Field Name
PAN_ID_0
R/W
R/W
Comments
Lower 8 bits of PAN address for address recognition, bits[7:0]
Table 8-24.
Bit
7:0
0x22 - PAN_ID_0
Reset
0
Field Name
PAN_ID_1
R/W
R/W
Comments
Higher 8 bits of PAN address for address recognition, bits[15:8]
Table 8-25.
Bit
7:0
0x23 - PAN_ID_1
Reset
0
Field Name
IEEE_ADDR_0
R/W
R/W
Comments
Lower 8 bits of IEEE address for address recognition, bits[7:0]
Table 8-26.
Bit
7:0
0x24 - IEEE_ADDR_0
Reset
0
Field Name
IEEE_ADDR_1
R/W
R/W
Comments
8 bits of IEEE address for address recognition, bits[15:8]
Table 8-27.
Bit
7:0
0x25 - IEEE_ADDR_1
Reset
0
Field Name
IEEE_ADDR_2
R/W
R/W
Comments
8 bits of IEEE address for address recognition, bits[23:16]
Table 8-28.
0x26 - IEEE_ADDR_2
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5131A-ZIGB-06/14/06
Bit
7:0
Field Name
IEEE_ADDR_3
Reset
0
R/W
R/W
Comments
8 bits of IEEE address for address recognition, bits[31:24]
Table 8-29.
Bit
7:0
0x27 - IEEE_ADDR_3
Reset
0
Field Name
IEEE_ADDR_4
R/W
R/W
Comments
8 bits of IEEE address for address recognition, bits[39:32]
Table 8-30.
Bit
7:0
0x28 - IEEE_ADDR_4
Reset
0
Field Name
IEEE_ADDR_5
R/W
R/W
Comments
8 bits of IEEE address for address recognition, bits[47:40]
Table 8-31.
Bit
7:0
0x29 - IEEE_ADDR_5
Reset
0
Field Name
IEEE_ADDR_6
R/W
R/W
Comments
8 bits of IEEE address for address recognition, bits[55:48]
Table 8-32.
Bit
7:0
0x2A - IEEE_ADDR_6
Reset
0
Field Name
IEEE_ADDR_7
R/W
R/W
Comments
Higher 8 bits of IEEE address for address recognition, bits[63:56]
Table 8-33.
Bit
7:4 3:1 0
0x2B - IEEE_ADDR_7
Reset
3 4 0
Field Name
MAX_FRAME_RETRIES MAX_CSMA_RETRIES
R/W
R/W R/W R/W
Comments
Number of retransmission attempts in ARET mode before the transaction gets cancelled. Number of retries in ARET mode to repeat the CSMA/CA procedures before the ARET procedure gives up. Reserved
Table 8-34.
Bit
7:0
0x2C - XAH_CTRL
Reset
234
Field Name
CSMA_SEED_0
R/W
R/W
Comments
Lower 8 bits of CSMA_SEED, bits[7:0] Seed for the random number generator in the CSMA/CA algorithm
Table 8-35.
0x2D - CSMA_SEED_0
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Bit
7:6 5:4 3
Field Name
MIN_BE
Reset
3 0
R/W
R/W R R/W
Comments
Minimum back-off exponent in the CSMA/CA algorithm. Reserved Use for address filtering within AACK mode (PAN coordinator) 1'd0: disable 1'd1: enable Higher 3 bits of CSMA_SEED, bits[10:8] Seed for the random number generator in the CSMA/CA algorithm
I_AM_COORD
0
2:0
CSMA_SEED_1
2
R/W
Table 8-36.
0x2E - CSMA_SEED_1
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9. Application Circuit
An application circuit with a single-ended RF connector is shown in Figure 9-1. An SMD-balun transforms the 100 differential RF inputs/outputs of the AT86RF230 to a 50 single ended RF port. The capacitors C1 and C2 form a DC-block. Power supply decoupling capacitors (CB2, CB4) are connected to the analog (28) and the digital supply pin (15). Capacitors CB1 and CB3 are load capacitors for the analog and digital voltage regulators. They ensure a stable operation of the low-voltage parts of the AT86RF230. All decoupling capacitors should be placed as close as possible to the AT86RF230 pin and need to have a low-resistance and low-inductive connection to ground to achieve the best performance. The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry connected to pins XTAL1 and XTAL2 form the crystal oscillator. To achieve the best accuracy and stability of the reference frequency, large stray capacitances should be avoided. Cross coupling of digital signals to the crystal pins or the RF pins can degrade system performance.
Designator Description
B1 CB1 CB2 CB3 CB4 CX1 CX2 C1 C2 XTAL SMD balun DC-blocking capacitor DC-blocking capacitor DC-blocking capacitor DC-blocking capacitor Crystal load capacitor Crystal load capacitor RF-coupling capacitor RF-coupling capacitor Crystal
Value
2.4 GHz 1 F 1 F 1 F 1 F 12 pF 12 pF 22 pF 22 pF CX-4025 16 MHz SX-4025 16 MHz
Manufacturer
Wuerth
Manuf. Part Number
748421245
ACAL Taitjen Siward
XWBBPL-F-1 A207-011
Table 9-1.
Bill of Materials
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AT86RF230
Vdd CB2 CX1 XTAL CX2
CB1 32 GND 31 GND 30 29 VDEC2 GND 28 VDD 27 GND 26 XTAL2 25 XTAL1
1 GND 2 GND C1 RF B1 C2 3 GND 4 RFP 5 RFN 6 GND 7 GND
IRQ 24
SEL 23
MOSI 22
AT86RF230
GND 21 MISO 20 SCLK 19 GND 18
VDEC1
VDEC1
8 RST GND GND
SLP_TR
CLKM 17 GND VDD
9
10
11
12
GND
13
14
15
16
CB3
CB4
Figure 9-1.
Application Schematic
Digital Interface
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10.
Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin Configuration
Name
GND GND GND RFP RFN GND GND RST GND GND SLP_TR GND VDEC1 VDEC1 VDD GND CLKM GND SCLK MISO GND MOSI SEL IRQ XTAL1 XTAL2 GND VDD VDEC2 GND GND GND
Type
Ground Ground Ground RF I/O RF I/O Ground Ground Digital input Ground Ground Digital input Ground De-coupling De-coupling Supply Ground Digital output Ground Digital input Digital output Ground Digital input Digital input Digital output Analog input Analog input Ground Supply De-coupling Ground Ground Ground
Description
Analog ground Analog ground Ground for RF signals Differential RF signal Differential RF signal Ground for RF signals Digital ground Chip reset pin, active low Digital ground Digital ground Controls sleep, transmit and receive mode, active high Digital ground Requires de-coupling capacitor Requires de-coupling capacitor Supply voltage Digital ground Master clock signal output to drive controller Digital ground SPI clock SPI data output (master input slave output) Digital ground SPI data input (master output slave input) SPI select signal, active low Interrupt request signal Crystal pin Crystal pin Analog ground Supply voltage Requires de-coupling capacitor Analog ground Analog ground Analog ground
Table 10-1.
AT86RF230 Pin List
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AT86RF230
10.1. Pin-out Diagram
GND GND GND VDEC2 VDD GND XTAL2 XTAL1 GND GND GND RFP RFN GND GND RST 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 AT86RF230 20 19 18 17 9 10 11 12 13 14 15 16 GND GND SLP_TR GND VDEC1 VDEC1 VDD GND IRQ SEL MOSI GND MISO SCLK GND CLKM
10.2. Decoupling
Correct functionality requires de-coupling of the internal power supply voltage (VDEC1/2). Capacitors of 1F (recommended value) shall be placed as close as possible to IC pins and shall be connected to ground with the shortest possible traces. Avoid long lines. It is recommended to insert additional 100 nF capacitors as close as possible at each VDD pin to ground.
10.3. Analog Pins
Pin
RFP/RFN XTAL1/XTAL2
Condition
VDC = 0.9V (TX) VDC = 20 mV (RX) at both pins CPAR = 3 pF VDC = 0.9V at both pins
Recommendation/Comment
Blocking is required if an antenna with a DC path to ground is used. Serial capacitance must be < 30 pF. Parasitic capacitance of the IC pins must be considered as additional parallel capacitance to the crystal.
Table 10-2.
Comments on RF Input/Output and Crystal Pins
10.4. RF Pins
A differential RF input provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks. At the board-level, the differential RF layout ensures the receiver sensitivity by rejecting any spurious signals originating from other digital ICs such as the micro-controller. The RF port is designed for a 100 differential load. A differential DC path between the RF pins is allowed. A DC path to ground or supply voltage is not allowed and requires capacitive coupling as indicated in Table 10-2.
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LNA
RX
RFP RFN
PA
TX
0.9V M0
CM Feedback RXTX
Figure 10-1.
Simplified RF Front-end Schematic
A simplified schematic of the RF front end is shown in Figure 10-1. RF port DC values depend on the operating mode. In TRX_OFF mode, the RF pins are pulled to ground, preventing a floating voltage larger than 1.8V which is not allowed for the internal circuitry. In receive mode, the RF input provides a low-impedance path to ground when transistor M0 pulls the inductor center tap to ground. A DC voltage drop of 20 mV across the on-chip inductor can be measured at the RF pins. In transmit mode, a regulation loop provides a common-mode voltage of 0.9V. Transistor M0 is off, allowing the PA to set the common-mode voltage. The common-mode capacitance at each pin to ground is limited to < 30 pF to ensure the stability of this common-mode feedback loop.
10.5. Digital Pins
Pulling resistors are connected to all digital input pins in transceiver state P_ON. Table 10-3 summarizes the pullup and pull-down configuration. In all other states there is no pull-up or pull-down resistor connected to any of the digital input pins.
Pin
RST SEL SCLK MOSI SLP_TR
H = pull-up, L = pull-down
H H L L L
Table 10-3.
Pull-up / pull-down configuration of digital input pins
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AT86RF230
11.
Ordering Information
Package
QN
Ordering Code
AT86RF230-ZU
Voltage Range
1.8 - 3.6V
Temperature Range
Industrial (-40 to 85 Lead-free/Halogen-free C C)
Package Type
QN
Description
32QN1, 32-lead 5.0 x5.0mm Body, 0.50mm Pitch, Quad Flat No-lead Package (QFN) Sawn
Note: T&R quantity 2,500. Please contact your local Atmel sales office for more detailed ordering information and minimum quantities.
12.
Soldering Information
Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C.
13.
Package Thermal Properties
Thermal Resistance
Velocity [m/s] 0 1 2.5 Theta ja [K/W] 40.9 35.7 32.0
47
5131A-ZIGB-06/14/06
14.
Package Drawing - 32QN1
D A
A3
E
Pin 1 Corner
A1 A2
Top View
Pin 1 Corner
Side View
COMMON DIMENSIONS (Unit of Measure = mm)
D2
SYMBOL D E
MIN
NOM 5.00 BSC 5.00 BSC
MAX
NOTE
E2
e
D2 E2 A
L
1.25 1.25 0.80 0.0 0.0 0.90 0.02 0.65 0.20 REF 0.30 0.40 0.50 BSC 0.18 0.23
3.25 3.25 1.00 0.05 1.00
A1 A2 A3
b
L e
0.50
Bottom View
Notes:
b
0.30
2
1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation VHHD-1, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
1/24/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 32QN1, 32-lead 5.0 x 5.0 mm Body, 0.50 mm Pitch, Quad Flat No Lead Package (QFN) Sawn DRAWING NO. 32QN1 REV. A
R
48
AT86RF230
5131A-ZIGB-06/14/06
AT86RF230
15.
[1] [2] [3] [4]
References
IEEE Std 802.15.4-2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method for electrostatic discharge sensitivity testing - Human Body Model (HBM) EIA / JESD22-A115-A: Electronic Industries Association, Electrostatic Discharge Sensitivity Testing - Machine Model (MM) ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing - Charged Device Model (CDM)
16.
1.0
Revisions
Date
2006-06-14
Revision
Description
Initial release
49
5131A-ZIGB-06/14/06
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5131A-ZIGB-06/14/06

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